Axelera AI unveils Titania, its third-gen AIPU chip

Dutch chip startup Axelera AI has unveiled the architecture of Titania, its third-generation AIPU chip. It targets the data center inference market, plans mass production in Q3 2027, and has already landed over 300 million dollars in orders.

Titania runs at 400W and uses two chiplets based on the third-gen D-IMC architecture. It is optimized for sparse MoE models, delivers 2.5 PFLOPS in FP8, and packs 128MB of shared SRAM cache.

The chip has 32 RISC-V cores built in, plus 128GB of LPDDR6 memory with a bandwidth of 2456GB/s. A 4U eight-card air-cooled server can run a 1.6T MoE model locally in FP4.

Axelera AI says Titania can reach 7 times the throughput per watt of today's servers, with total costs down to one twentieth. It runs DeepSeek R1 fast enough to match NVIDIA's liquid-cooled Vera Rubin NVL72 rack.