Qualcomm unveils Dragonfly data center lineup with C1000 CPU and AI300 accelerator

Qualcomm announced its full Dragonfly data center solution at an investor day, including the new HBC architecture, C1000 CPU, and AI300 inference accelerator, along with chip design services and interconnect offerings.

The HBC (High Bandwidth Compute) architecture uses a disaggregated design with TSV-stacked LPDDR memory, offering better energy efficiency and effective bandwidth than HBM-based systems. The AI250 accelerator with HBC Gen 1 achieves 133TB/s memory read/write speed, with commercial sampling expected by mid-2027.

The Dragonfly C1000 CPU is built for data center workloads, supporting over 250 Oryon cores at over 5GHz, delivering more than double the energy efficiency of competitors, and is set for 2028 release. The AI300, a third-gen inference platform with HBC Gen 2, triples the effective memory bandwidth of AI250 and will start commercial sampling in 2028. Qualcomm also highlighted end-to-end chip design capabilities and 800G/1.6T interconnect tech.